1. Field of the Invention
The present invention relates to a semiconductor device having a package structure and a method of manufacturing the same.
This application is counterpart of Japanese patent applications, Serial Number 404987/2003, filed Dec. 3, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
There has recently been an increasingly demand for a reduction and thinning of an outer size (package size) of a semiconductor device mounted to electronic equipment such as a portable device. With its demand, there has been proposed a CSP (Chip Size Package) corresponding to a semiconductor device packaged to an outer size substantially identical to an outer size of a semiconductor chip.
In terms of a reduction in the manufacturing cost, attention is now given, as one form of CSP, to a WCSP (WaferLevel Chip Size Package or WaferLevel Chip Scale Package) obtained by fractionalization through the use of dicing or the like after processes up to an external terminal forming process have been completed in a wafer state (see, for example, a patent document 1).
There is also known a bear chip having a configuration equipped with through portions in which conductors are formed on inner wall surfaces of through holes that pass between the obverse and reverse sides of a substrate (see, for example, a patent document 2). Since the transmission of a signal between the front and back surfaces of the bear chip is enabled by virtue of the through portion, laminated packages laminated in plural form in the direction of thickness of the bear chip can be configured.
Such through portions are normally formed in peripheral edge portions, i.e., dicing areas of chips cut out by dicing using a blade. This is because since there is a need to lay out circuit elements in the high density in a circuit element forming area (also called “active area”) surrounded by the dicing areas, there is no space for each through portion, and the through portions are formed in the active area, thereby causing the fear of the scale-up of a chip size and an increase in manufacturing cost. Incidentally, the dicing areas used herein means surfaces to be cut off by dicing and areas located in the neighborhood thereof.
Patent Document 1
Japanese Laid Open Patent Application No. 2002-110951
Patent Document 2
Japanese Laid Open Patent Application No. 2000-243900
However, cracks and chipping-off are easy to take place in each dicing area due to the shock of the blade at the dicing. Therefore; there was a fear that the through portions formed in the dicing area were damaged due to the occurrence of such cracks and chipping-off or the like, thereby causing degradation of reliability. Particularly when micro cracks has occurred in each dicing area, it was difficult to discriminate the through portions subjected to the damage from outward appearance. Thus, it was very difficult to manage the quality of each chip.
In the wafer's dicing used up to now, the back surface of a wafer was fixed onto a dicing sheet and thereafter the wafer was cut off from the exposed surface of the wafer by use of a blade. Therefore, the occurrence of cracks and chipping-off greatly take place on the back side of the wafer in particular due to wafer's vibrations developed by the blade, thereby causing the damage of the through portions.
Therefore, three has been proposed a method of expanding the spacing or interval of a through portion between adjacent chips and ensuring it sufficiently in order to avoid the damage of the through portions due to the cracks and chipping-off. Since, however, the number of chips cuttable per wafer is reduced due to the expansion of the width of each dicing area, the manufacturing cost will increase.
Although there has heretofore been proposed a method utilizing heat fusion using laser light as the dicing method using the laser light, there are a lot of problems to be solved such as thermal distortion, contamination, etc.